Enhancement of SAR Algorithm for Analog to Digital Converter

Nowadays, the development of the IC technology resulted in a growth of digital systems. Thus, Analog to Digital converters have become important. The important criteria of an ADC are resolution, speed and power. Among them, speed plays an important role to be enabling faster and more reliable for data processing. This paper describes a successive approximation ADC that uses a charge-redistribution digitalto-analog converter (DAC) designed to achieve a good accuracy and high speed. However, conventional Successive Approximation Register (SAR) ADC can get the final conversion result through a total of "n" time comparison to convert "n" bits digital code from an analog. This makes SAR ADCs that is not affected for high speed applications. To overcome this problem, the new algorithm of SAR ADC which can reduce the number of conversion step is proposed. This algorithm enhances the speed of SAR ADC system that to be apply in high speed application.